1. Field of the Invention
Embodiments relate to powering up a block alterable memory device.
2. Background
Block-alterable memories, such as flash memories, are often used for applications in which non-volatility and programmability are desired. Typically such memory devices include a number of separately erasable blocks. To update a particular block, it is first erased and data is then written to the erased block. Different block-alterable memories exist, such as NOR and NAND flash designs, both of which use absolute physical addressing to address blocks within user memory space.
Users desire that block-alterable memories accurately store and retrieve data quickly. While data may be read from flash memories rapidly, erasing flash memory takes much longer. Erase times for conventional NOR flash memories are on the order of hundreds of milliseconds while and on the order of milliseconds for NAND flash memories. While software techniques are often implemented to accommodate long erase times, these techniques involve complex software and are not always capable of hiding the impact of relatively long erase times from a user.
In some of the block alterable memories, information which defines whether the block is in use, and its assigned logical address, if any, is stored in the block itself. By altering this status information, a memory block can be quickly mapped into or out of the memory address space, this giving the illusion of nearly zero block erase time. However, the status information is thus scattered throughout the memory blocks and requires the onboard memory controller to poll each block for the status information whenever a new block is to be allocated. Thus, memory speed during operation is compromised.